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LTM4611 Ultralow VIN, 15A DC/DC Module Regulator FeaTures
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DescripTion
The LTM4611 is a high density 15A output, switch mode DC/DC buck converter power supply capable of operating from very low voltage input supplies. Included in the package are the buck switching controller, power FETs, inductor and loop-compensation components. The LTM4611 delivers up to 15A continuous current at high efficiency from an input voltage of 1.5VIN up to 5.5VIN. The output voltage is set between 0.8V and 5V by a resistor. Only a few input and output capacitors are needed. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. The device supports frequency synchronization, multiphase/current sharing operation, Burst Mode operation and output voltage tracking for supply rail sequencing. The LTM4611 is available in a thermally enhanced 15mm x 15mm x 4.32mm LGA package. The LTM4611 is PB-free and RoHS compliant.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, PolyPhase and Module are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210.
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Complete Switch Mode Power Supply Input Voltage Range: 1.5V to 5.5V 15A DC Output Output Voltage Range: 0.8V to 5V 1.5% Total DC Output Error Differential Remote Sensing for Precision Regulation Current Mode Control/ Fast Transient Response Overcurrent Foldback Protection Parallel Multiple LTM(R)4611s for Current Sharing Frequency Synchronization Selectable Pulse-Skipping or Burst Mode(R) Operation Soft-Start/Voltage Tracking Up to 94% Efficiency Output Overvoltage Protection Small 15mm x 15mm x 4.32mm LGA Package
applicaTions
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Telecom Servers and Networking Equipment Storage and ATCA Cards General Purpose Point of Load Regulation
Typical applicaTion
1.5VIN to 5.5VIN, 15A Step-Down DC/DC Module (R) Regulator
VIN 1.5V TO 5.5V 96 22F 3 CSS 0.1F TRACK/SS LTM4611 RUN MODE_PLLIN VIN PGOOD VOUT VFB VOUT_LCL DIFFVOUT VOSNS SGND GND VOSNS
+ -
Efficiency vs Load Current
94
EFFICIENCY (%)
CFF*
VOUT** STEP-DOWN 15A 100F* 4
92 90 88 86 84 82 5VIN, 3.3VOUT 3.3VIN, 2.5VOUT 2.5VIN, 1.5VOUT 2.5VIN, 1.2VOUT 3.3VIN, 1VOUT 1.5VIN, 0.9VOUT 5VIN, 1VOUT
CP*
4611 TA01
RFB**
*SEE TABLE 5 **SEE TABLE 1
80 78 0 5 10 LOAD CURRENT (A) 15
4611 TA01b
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LTM4611 absoluTe MaxiMuM raTings
(Note 1)
pin conFiguraTion
1 A 2 3
Terminal Voltages VIN ........................................................... -0.2V to 6V VOUT with DIFF AMP....-0.1V to the Lesser of (VIN + 0.1V) or 4V VOUT without DIFF AMP ..-0.1V to the Lesser of (VIN + 0.1V) or 5.5V RUN, INTVCC, VOUT_LCL ..........................................6V MODE_PLLIN, PLLFLTR/fSET, TRACK/SS, VOSNS-, VOSNS+, PGOOD ................................................. -0.3V to 5.5V COMP VFB ............................................. -0.3V to 2.7V , Terminal Currents DIFFVOUT............................................. -10mA to 1mA Temperatures Operating Junction Temperature Range (Note 2) ............................................ -40C to 125C Storage Temperature Range .............. -55C to 125C Peak Solder Reflow Body Temperature (Note 3) ............................................................ 250C
VIN
4
5
TOP VIEW INTVCC TRACK/SS MODE_PLLIN RUN COMP
6 7 8 9 10 11 12
VIN
B C D E F G H J
PLLFLTR/fSET MTP1-9 INTVCC VFB PGOOD SGND VOSNS+ DIFFVOUT VOUT_LCL VOSNS- LGA PACKAGE 133-LEAD (15mm 15mm 4.32mm)
GND
VOUT
K L M
TJ(MAX) = 125C JCtop = 26C/W, JCbottom = 2.3C/W, JB = 10C/W, JA = 14C/W VALUES DETERMINED PER JESD51-12 WEIGHT = 2.6 GRAMS
orDer inForMaTion
LEAD FREE FINISH LTM4611EV#PBF LTM4611IV#PBF TRAY LTM4611EV#PBF LTM4611IV#PBF PART MARKING* LTM4611V LTM4611V PACKAGE DESCRIPTION 133-Lead (15mm x 15mm x 4.32mm) LGA 133-Lead (15mm x 15mm x 4.32mm) LGA TEMPERATURE RANGE -40C to 125C -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
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LTM4611 elecTrical characTerisTics
SYMBOL VIN VRUN VRUNHYS VRUN(FLOAT) IRUN(UP,1V) IRUN(UP,1.5V) IRUN(DOWN,5V) IQ PARAMETER Input DC Voltage RUN Pin On Threshold RUN Pin On Hysteresis RUN Pin Voltage when Floating RUN Pin Pull-Up Current (RUN = 1V) RUN Pin Pull-Up Current (RUN = 1.5V) RUN Pin Pull-Down Current (RUN = 5V) Input Supply Bias Current VOUT = 1.5V, Burst Mode Operation, IOUT = 0.1A VOUT = 1.5V, Pulse-Skipping Mode, IOUT = 0.1A VOUT = 1.5V, Switching Continuous, IOUT = 0.1A Shutdown, RUN = 0V VIN = 2.5V, VOUT = 1.5V, IOUT = 15A VIN = 3.3V, VOUT = 1.5V, IOUT = 15A VIN = 5V, VOUT = 1.5V, IOUT = 15A VIN = 1.5V, VOUT = 0.8V, IOUT = 15A Utilizing DIFF_AMP, RFB = Not Used, VIN = 1.5V to l 5.5V, IOUT = 0A to 15A (Note 4), RFB Electrically Floating, MODE_PLLIN = GND (Example See Figure 21) (Example See Figure 20) VOUT = VFB (Note 4) VOUT = VFB, VIN from 1.5V to 5.5V, IOUT = 0A VOUT = 1.5V, IOUT = 0A to 15A, VIN = 3.3V (Note 4) IOUT = 0A, COUT = 100F x4 X5R Ceramic, VIN = 3.3V, VOUT = 1.5V COUT = 100F x4 X5R Ceramic, VOUT = 1.5V, IOUT = 0A, VIN = 3.3V, CSS = 1nF COUT = 100F x4 X5R Ceramic, No Load, CSS = 1nF, VIN = 3.3V, VOUT = 1.5V Load: 0% to 50% to 0% of Full Load VIN = 3.3V, VOUT = 1.5V, COUT = 100F x4 X5R Ceramic, CFF = 100pF Load: 0% to 50% to 0% of Full Load VIN = 3.3V, VOUT = 1.5V, COUT = 100F x4 X5R Ceramic, CFF = 100pF VIN = 5V, VOUT = 1.5V VIN = 3.3V, VOUT = 1.5V
l
The l denotes the specifications which apply over the full internal operating junction temperature range, otherwise specifications are at TA = 25C, VIN = 3.3V, per the typical application in Figure 21.
CONDITIONS
l
MIN 1.5 1.1 3.4
TYP
MAX 5.5
UNITS V V mV V A A nA mA mA mA mA A A A A
Input Specifications VRUN Rising
l
1.22 80 3.65 1.1 10 1 70 140 145 1.1 10.4 7.9 5.3 10.2
1.35 4
IS(VIN)
Input Supply Current
Output Specifications VOUT(DC) VOUT(RANGE) IOUT(DC) VOUT (Line) VOUT VOUT (Load) VOUT VOUT(AC) VOUT(START) tSTART VOUTLS tSETTLE IOUT(PK) Output Voltage, Total Variation with Line and Load Utilizing DIFF_AMP Not Utilizing DIFF_AMP Output Continuous Current Range Line Regulation Accuracy Load Regulation Accuracy Output Ripple Voltage Turn-On Overshoot Turn-On Time Peak Deviation for Dynamic Load 0.785 0.781 0.797 0.797 0.809 0.813 3.7 5.4 0 15 0.3 0.2 8 5 500 60 0.5 V V V V A % % mVP-P mV s mV
l
Settling Time for Dynamic Load Step Output Current Limit
40
s
30 30
A A
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LTM4611 elecTrical characTerisTics
SYMBOL Control Section VFB IFB VOVL ITRACK/SS tON(MIN) RFBHI VOSNS+, VOSNS - CM RANGE DIFFVOUT Range VOS AV VPGOOD Feedback Overvoltage Lockout Track Pin Soft-Start Pull-Up Current Minimum On-Time Resistor Between VOUT_LCL and VFB Pins Common Mode Input Range DIFF_AMP Output Voltage Range DIFF_AMP Input Offset Voltage Magnitude DIFF_AMP Differential Gain PGOOD Trip Level VFB with Respect to Set Output VFB Ramping Positive, PGOOD Transitioning VFB Ramping Positive, PGOOD Transitioning VFB Ramping Negative, PGOOD Transitioning VFB Ramping Negative, PGOOD Transitioning -10 5 5 -10 VIN = 3.3V, Run > 1.5V VIN = 3.3V, DIFFVOUT Load = 100k
l l
The l denotes the specifications which apply over the full internal operating junction temperature range, otherwise specifications are at TA = 25C, VIN = 3.3V, per the typical application in Figure 21.
PARAMETER Voltage at VFB Pin CONDITIONS IOUT = 0A, VOUT = VFB
l
MIN 0.783 0.84 0.9
TYP 0.797 -10 0.87 1.4 90
MAX 0.811 0.89 1.9
UNITS V nA V A ns
TRACK/SS = 0V (Note 5)
60.05 0 0
60.40
60.75 INTVCC - 1 INTVCC 1.25 2
k V V mV mV V/V
1 -7.5 7.5 7.5 -7.5 2 3 100 VOSNS+ to GND 1.5V < VIN < 5.5V ICC = 0 to 50mA VIN = 3.3V, VOUT = 1.5V, 0.85V PLLFLTR/fSET 2.0V 280 360 19.9 4.8 20.0 5 0.5 835 710 20.1 5.2 -5 10 10 -5
% % % % V/s MHz dB k V % kHz kHz
SR GBP CMRR RIN VINTVCC VINTVCC Load Reg fS fSYNC
DIFF_AMP Slew Rate DIFF_AMP Gain-Bandwidth Product DIFF_AMP Common Mode Rejection DIFF_AMP Input Resistance Internal VCC Voltage INTVCC Load Regulation Output Ripple Voltage Frequency SYNC Capture Range
INTVCC Linear Regulator
Oscillator and Phase-Locked Loop
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LTM4611 elecTrical characTerisTics
SYMBOL PARAMETER PLLFLTR/fSET(FLOAT) PLLFLTR/fSET Open-Circuit Voltage Frequency Nominal Nominal Frequency Frequency Low Frequency High IPLLFLTR RMODE(PLLIN) VIH VIL Mode_PLLIN Clock Lowest Frequency Highest Frequency PLLFLTR Sourcing Capability Sinking Capability Mode_PLLIN Input Resistance Clock Input Level High Clock Input Level Low Clock Input Duty Cycle Range 40 50 2.0 0.6 60
The l denotes the specifications which apply over the full internal operating junction temperature range, otherwise specifications are at TA = 25C, VIN = 3.3V, per the typical application in Figure 21.
CONDITIONS PLLFLTR/fSET Pin Voltage When Floating PLLFLTR/fSET Floating PLLFLTR/fSET = 0.85V PLLFLTR/fSET = 2.0V Mode_PLLIN Frequency > fOSC Mode_PLLIN Frequency < fOSC MIN TYP 1.23 500 330 780 -13 13 250 MAX UNITS V kHz kHz kHz A A k V V %
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4611 is tested under pulsed load conditions such that TJ TA. The LTM4611E is guaranteed to meet performance specifications over the 0C to 125C operating junction temperature (TJ) range. Specifications over the full -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4611I is guaranteed to meet specifications over the full -40C to 125C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.
Note 3: Consistent with Pb-free 260C peak IR reflow soldering profiles. See Application Note 100. Note 4: See output current derating curves for different VIN, VOUT and TA. Note 5: The minimum on-time condition is specified for a peak-to-peak inductor ripple current of ~40% of IMAX Load. (See the Typical Applications section)
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LTM4611 Typical perForMance characTerisTics
95
Efficiency vs Load Current at 1.5VIN, Forced Continuous Mode
1.2VOUT 1.0VOUT 0.9VOUT 0.8VOUT EFFICIENCY (%)
95
Efficiency vs Load Current at 1.8VIN, Forced Continuous Mode
95
Efficiency vs Load Current at 2.5VIN, Forced Continuous Mode
90 EFFICIENCY (%)
90 EFFICIENCY (%)
90
85
85 1.5VOUT 1.2VOUT 1.0VOUT 0.9VOUT 0.8VOUT 0 3 9 12 6 OUTPUT CURRENT (A) 15
4611 G02
85
80
80
80 1.8VOUT 1.5VOUT 1.2VOUT 0 3 1.0VOUT 0.9VOUT 0.8VOUT 15
4611 G03
75
0
3
9 12 6 OUTPUT CURRENT (A)
15
4611 G01
75
75
9 12 6 OUTPUT CURRENT (A)
Efficiency vs Load Current at 3.3VIN, Forced Continuous Mode
95 95
Efficiency vs Load Current at 5VIN, Forced Continuous Mode
Burst Mode Efficiency
95 90 85 80 75 70 65 60 55 50 45 40 35 30 0.1 3.3VIN TO 1.5VOUT
90 EFFICIENCY (%) EFFICIENCY (%)
90 EFFICIENCY (%)
5VIN TO 1VOUT
85
85
80
75
2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0 3
80 1.0VOUT 0.9VOUT 0.8VOUT 15
4611 G04
9 12 6 OUTPUT CURRENT (A)
75
3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 0 3
1.2VOUT 1.0VOUT 0.9VOUT 0.8VOUT 15
4611 G05
9 12 6 OUTPUT CURRENT (A)
1 OUTPUT CURRENT (A)
10
4611 G14
Pulse-Skipping Mode Efficiency
95 90 85 80 75 70 65 60 55 50 45 40 35 30 0.1
1V Transient Response, 3.3VIN
1V Transient Response, 5VIN
EFFICIENCY (%)
3.3VIN TO 1.5VOUT 5VIN TO 1VOUT
VOUT 50mV/DIV AC-COUPLED ILOAD 5A/DIV
4611 G06 20s/DIV VIN = 3.3V, VOUT = 1V, USING DIFF AMP 4 100F CERAMIC OUTPUT CAPACITORS , CFF = 47pF CP = NONE 7.5A LOAD STEP AT 7.5A/s
VOUT 50mV/DIV AC-COUPLED ILOAD 5A/DIV
4611 G07 20s/DIV VIN = 5V, VOUT = 1V, USING DIFF AMP 4 100F CERAMIC OUTPUT CAPACITORS , CFF = 47pF CP = NONE 7.5A LOAD STEP AT 7.5A/s
1 OUTPUT CURRENT (A)
10
4611 G15
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LTM4611 Typical perForMance characTerisTics
3.3V Transient Response, 5VIN
VOUT 50mV/DIV AC-COUPLED ILOAD 5A/DIV
4611 G08 20s/DIV VIN = 5V, VOUT = 3.3V, USING DIFF AMP 2 100F CERAMIC OUTPUT CAPACITORS , CFF = 10pF CP = NONE 7.5A LOAD STEP AT 7.5A/s
Start-Up, No Load
VIN 1V/DIV VOUT 500mV/DIV ILOAD 5A/DIV IIN 5A/DIV
4611 G09 1ms/DIV VIN = 3.3V, VOUT = 1.5V, NO LOAD 3 22F CERAMIC INPUT CAPACITORS CSS = 10nF 4 100F CERAMIC OUTPUT CAPACITORS , CFF = 33pF CP = 10pF
Start-Up, 15A Load
VIN 1V/DIV VOUT 500mV/DIV IIN 1A/DIV
4611 G12 1ms/DIV VIN = 3.3V, VOUT = 1.5V, 100m LOAD 3 22F CERAMIC INPUT CAPACITORS CSS = 10nF 4 100F CERAMIC OUTPUT CAPACITORS , CFF = 33pF CP = 10pF
Start-Up, Pre-Bias
VOUT 500mV/DIV ILOAD 2mA/DIV IIN 1A/DIV RUN 5V/DIV
4611 G13 2ms/DIV VIN = 3.3V, VOUT = 1.5V, 0.75V PRE-BIAS LOAD 3 22F CERAMIC INPUT CAPACITORS CSS = 10nF 4 100F CERAMIC OUTPUT CAPACITORS , CFF = 33pF CP = 10pF
Short-Circuit, 15A
VOUT 500mV/DIV VOUT 500mV/DIV
Short-Circuit, No Load
IIN 2A/DIV 20s/DIV VIN = 3.3V, VOUT = 1.5V 15A LOAD PRIOR TO SHORT
4611 G10
IIN 1A/DIV 20s/DIV VIN = 3.3V, VOUT = 1.5V NO LOAD PRIOR TO SHORT
4611 G11
pin FuncTions
VIN: (A1-A6, B1-B6, C1-C6) Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. VOUT: (J1-J10, K1-K11, L1-L11, M1-M11) Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 5. GND: (B7, B9, C7, C9, D1-D6, D8, E1-E7, E9, F1-F9, G1-G9, H1-H9) Power Ground Pins for Both Input and Output Returns. PGOOD: (F11, G12) Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage exceeds a 5% regulation window. Both pins are tied together internally. SGND: (G11, H11, H12) Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See the layout guidelines in Figure 17. MODE_PLLIN: (A8) Forced Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to GND to force continuous mode operation. Connect to INTVCC to enable pulse-skipping mode operation. Leaving the pin floating will enable Burst Mode operation. A clock on this pin will enable synchronization with forced continuous operation. See the Applications Information section.
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LTM4611 pin FuncTions
PLLFLTR/fSET: (B12) Phase-Locked Loop Lowpass Filter for the Internal Phase Detector. LTM4611's default switching frequency is 500kHz. Its switching frequency can be increased by connecting a resistor from this pin to INTVCC, or decreased by connecting a resistor from this pin to SGND. See the Applications Information section. VFB: (F12) The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT_LCL with a 60.4k precision resistor. Different output voltages can be programmed with an additional resistor between the VFB and GND pins. In PolyPhase(R) operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. TRACK/SS: (A9) Output Voltage Tracking Pin and SoftStart Inputs. The pin has a 1.4A pull-up current source. A capacitor from this pin to ground will set a soft-start ramp rate. In tracking, the regulator output can be tracked to a different voltage. The different voltage is applied to a voltage divider then the slave output's track pin. This voltage divider is equal to the slave output's feedback divider for coincidental tracking. Tie all TRACK/SS pins together for parallel operation. See the Applications Information section. COMP: (A11) Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Tie all COMP pins together for parallel operation. The device is internally compensated. RUN: (A10) Run Control Pin. A voltage above 1.35V will turn on in the module. The VIN undervoltage lockout (UVLO) of the LTM4611 must be set with resistor networks from VIN to RUN and optionally from RUN to GND. Tie all RUN pins together for parallel operation. INTVCC: (A7, D9) Internal 5V LDO for Driving the Control Circuitry and the Power MOSFET Drivers. Both pins are internally connected. VOUT_LCL: (L12) This pin connects to VOUT through a 1M resistor and to VFB with a 60.4k resistor. The remote sense amplifier output DIFFVOUT is connected to VOUT_LCL, and drives the 60.4k top feedback resistor in remote sensing applications. When the remote sense amplifier is used, the DIFF_VOUT effectively eliminates the 1M from VOUT to VOUT_LCL. When the remote sense amplifier is not used, then connect VOUT_LCL to VOUT directly. VOSNS+: (J12) (+) Input to the Remote Sense Amplifier. This pin connects to the output remote sense point. The remote sense amplifier is used for VOUT 3.7V. For VOUT > 3.7V, tie VOSNS+ to GND to rail the output of the remote sense amplifier. VOSNS -: (M12) (-) Input to the Remote Sense Amplifier. This pin connects to the ground remote sense point. The remote sense amplifier is used for VOUT 3.7 V. For VOUT > 3.7V, tie VOSNS - to INTVCC to rail the output of the remote sense amplifier. DIFFVOUT : (K12) Output of the Remote Sense Amplifier. This pin connects to the VOUT_LCL pin for remote sense applications. Otherwise float when not used. MTP1:A12, MTP2:B11, MTP3:C10, MTP4:C11, MTP5: C12, MTP6:D10, MTP7:D11, MTP8:D12, MTP9:E12: Extra mounting pads used for increased solder integrity strength. Leave electrically open circuit.
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LTM4611 block DiagraM
INTVCC VOUT_LCL VIN R1 >1.35V = ON <1.1V = OFF ABS MAX = 6V 1M VOUT 10k PGOOD VIN 2F
RUN COMP 0.5% 60.4k
POWER BIAS GENERATOR
+
VIN 1.5V TO 5.5V CIN
R2
AS NEEDED
INTERNAL COMP SGND VFB PLLFLTR/fSET 240k
M1 0.2H POWER CONTROL M2 VOUT 10F GND VOUT 1V 15A COUT
+
INTERNAL LOOP FILTER TRACK/SS CSS MODE_PLLIN INTVCC C
10k
INTVCC
10k
VOSNS- VOSNS+
Figure 1. Simplified LTM4611 Block Diagram
Decoupling reQuireMenTs
SYMBOL CIN COUT PARAMETER External Input Capacitor Requirement (VIN = 1.5V to 5.5V, VOUT = 1V) External Output Capacitor Requirement (VIN = 1.5V to 5.5V, VOUT = 1V)
TA = 25C. Use Figure 1 configuration.
MIN TYP 66 MAX UNITS F
CONDITIONS IOUT = 15A IOUT = 15A
- +
-
+
10k 10k
DIFFVOUT
4611 F01
400
F
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LTM4611 operaTion
Power Module Description The LTM4611 is a high performance single output standalone nonisolated switching mode DC/DC power supply. It can provide a 15A output with few external input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.8VDC to 5VDC over a 1.5V to 5.5V input range. The typical application schematic is shown in Figure 21. The LTM4611 has an integrated constant-frequency current mode regulator, power MOSFETs, 0.2H inductor and other supporting discrete components. The nominal switching frequency range is from 330kHz to 780kHz, and the default operating frequency is 500kHz. For switching noise-sensitive applications, it can be externally synchronized from 360kHz to 710kHz. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4611 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. An internal overvoltage monitor protects the output voltage in the event of an overvoltage >7.5%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output is cleared. Pulling the RUN pin below 1.1V forces the regulator into a shutdown state. The TRACK/SS pin is used for programming the output voltage ramp and voltage tracking during start-up. See the Application Information section. The LTM4611 is internally compensated to be stable over all operating conditions. Table 5 provides a guideline for input and output capacitances for several operating conditions. The Linear Technology Module Power Design Tool will be provided for transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to ground. A remote sense amplifier is provided for accurately sensing output voltages 3.7V at the load point. Multiphase operation can be easily employed with the synchronization inputs using an external clock source. See the Typical Applications. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE_PLLIN pin. These light-load features will accommodate battery operation. Efficiency graphs are provided for light-load operation in the Typical Performance Characteristics section.
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0
LTM4611 applicaTions inForMaTion
The typical LTM4611 application circuit is shown in Figure 21. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 5 for specific external capacitor requirements for particular applications. VIN to VOUT Step-Down Ratios There are restrictions in the VIN to VOUT step-down ratio that can be achieved for a given input voltage. The VIN to VOUT minimum dropout is still a function of its load current at very low input voltages. A dropout voltage of 300mV from input to output of LTM4611 is achievable at 15A load, but reflected input voltage ripple and noise should be taken into consideration in such applications. Additionally, the transient-handling capability of the source supply feeding LTM4611 can become an important factor in truly achieving ultralow dropout at high output current. For example, VIN can sag or overshoot dramatically when LTM4611 responds to heavy transient step loads on its output, if insufficient input bypass capacitance is used in combination with a sluggish source supply. When VOUT is expected to be within 600mV of VIN, or when the caliber of the source supply is in question, it is recommended to evaluate the amount and quality of input bypass capacitance needed to maintain one's target dropout voltage with the source supply that will be used in the end application. Demo Board DC1588A can be used for such evaluation. At very low duty cycles the minimum specified on-time must be maintained. See the Frequency Adjustment section and temperature derating curves. To prevent overstress to the power bias generator, do not ramp up VIN at a rate exceeding 5V/s (in practice, it is difficult to violate this guideline.) There is no restriction on how rapidly VIN may be discharged. Output Voltage Programming The PWM controller has an internal 0.8V 1.75% reference voltage over temperature. As shown in the Block Diagram, a 60.4k internal feedback resistor connects the VOUT_LCL and VFB pins together. When the remote sense amplifier is used, then DIFFVOUT is connected to the VOUT_LCL pin. If the remote sense amplifier is not used, then VOUT_LCL connects to VOUT. The output voltage will default to 0.8V with no feedback resistor. Adding a resistor RFB from VFB to GND programs the output voltage: VOUT = 0.8V * 60.4k +R FB R FB
1.2V 121 1.5V 68.1 1.8V 47.5 2.5V 28.0 3.3V 19.1 5.0V 11.5
Table 1. VFB Resistor Table vs Various Output Voltages
VOUT 0.8V 1.0V 243 RFB (k) Open
For parallel operation of N LTM4611s, the following equation can be used to solve for RFB: RFB = 60.4k / N VOUT -1 0.8V
Tie the VFB pins together for each parallel output. The COMP, TRACK/SS, VOUT_LCL, and RUN pins must also be tied together as shown in Figures 18 and 19. For parallel applications, best noise immunity can be achieved by placing capacitors of value CP from VFB to GND, and value CFF from VOUT to VFB, local to each Module. If space limitations impede realizing this, then placement of capacitors of value N * CP from VFB to GND, and value N * CFF from VOUT to the bussed VFB signal, can suffice. Input Capacitors The LTM4611 module should be connected to a low AC impedance DC source. Additional input capacitors are needed for the RMS input ripple current rating. The ICIN(RMS) equation which follows can be used to calculate the input capacitor requirement. Typically 22F X7R ceramics are a good choice with RMS ripple current ratings of ~2A each. A 100F to 150F surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed.
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LTM4611 applicaTions inForMaTion
For a buck converter, the switching duty cycle can be estimated as: V D = OUT VIN Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) % * D *(1- D) Burst Mode Operation The LTM4611 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply leave the MODE_PLLIN pin floating. During Burst Mode operation, the peak current of the inductor is set to approximately 33% of the maximum peak current value in normal operation even though the voltage at the ITH pin indicates a lower value. The voltage at the ITH pin drops when the inductor's average current is greater than the load requirement. As the ITH voltage drops below 0.5V, the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In this sleep mode, the internal circuitry is partially turned off, reducing the LTM4611's quiescent current while the load current is supplied by the output capacitors. When the output voltage drops-causing ITH to rise-the internal sleep line goes low and the LTM4611 resumes normal operation. The next oscillator cycle turns on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4611 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTVCC enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be
In the above equation, % is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor or a Polymer capacitor. Output Capacitors The LTM4611 is designed for low output voltage ripple noise. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be the low ESR tantalum capacitor, the low ESR Polymer capacitor or ceramic capacitors. The typical output capacitance range is from 200F to 800F. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is required. Table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 7A/s transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 5 matrix, and the Linear Technology Module Power Design Tool will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology Module Power Design Tool can calculate the output ripple reduction as the number of implemented phase's increases by N times.
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LTM4611 applicaTions inForMaTion
enabled by tying the MODE_PLLIN pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the ITH voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4611's output voltage is in regulation. Multiphase Operation For outputs that demand more than 15A of load current, multiple LTM4611 devices can be paralleled to provide more output current without increasing input and output voltage ripples. The MODE_PLLIN pin allows the LTM4611 to be synchronized to an external clock (between 360kHz to 710kHz) and the internal phase-locked loop allows the LTM4611 to lock onto input clock phase as well. The PLLFLTR/fSET pin has the onboard loop filter for the PLL. See Figures 18 and 19 for a synchronizing example circuit. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and
0.60 0.55 0.50 0.45 RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY FACTOR (VOUT/VIN)
4617#3EM F02
the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used. See Application Note 77. The LTM4611 device is an inherently current mode controlled device, so parallel modules will have good current sharing. This will balance the thermals on the design. Tie the COMP, VOUT_LCL and VFB pins of each LTM4611 together to share the current evenly. In addition, tie the respective TRACK/SS and RUN pins of paralleled LTM4611 devices together, to ensure proper start-up and shutdown behavior. Figures 18 and 19 show schematics of LTM4611 devices operating in parallel. Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases (see Figure 2).
1 PHASE 2 PHASE 3 PHASE 4 PHASE 6 PHASE
Figure 2. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Modules (Phases)
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LTM4611 applicaTions inForMaTion
PLL, Frequency Adjustment and Synchronization The default switching frequency of the LTM4611-with PLLFLTR/fSET left floating-is 500kHz, nominally. The PLLFLTR/fSET pin is driven to 1.23V through a high impedance (>350k) network. If desired, a resistor (RfSET ) can be connected from the PLLFLTR/fSET pin to INTVCC to increase the switching frequency to as high as 780kHz, nominally. Alternatively, RfSET can instead be connected from PLLFLTR/fSET to signal ground (SGND) to decrease the switching frequency to as low as the minimum specified value of 330kHz, nominally. In practical terms, however, be advised that switching frequencies below 400kHz may be of limited benefit due to the high inductor ripple currents associated with that operating condition. See Figure 3. There exists a fundamental trade-off between switch mode DC/DC power conversion efficiency and switching frequency: higher operating module switching frequency enables the smallest overall solution size (minimized output capacitance) for a given application; whereas, lower switching frequency enables the highest efficiency for a given application (to the extent that peak and RMS inductor currents can be supported), but requires more output capacitance to maintain comparable output voltage ripple and noise characteristics. The LTM4611 can be synchronized from 360kHz to 710kHz with an input clock that has a high level above 2V and a low level below 0.6V. Again in practical terms, be advised that switching frequencies below 400kHz may be of limited
2.05 1.91 PLLFLTR/fSET PIN VOLTAGE (V) 1.78 1.64 1.50 1.37 1.23 1.09 0.96 0.82 0.68 0.55 RfSET CONNECTED TO GND RfSET CONNECTED TO INTVCC RfSET NOT USED 800 750 700 650 600 550 500 450 400 350 SWITCHING FREQUENCY (kHz)
benefit due to the high inductor ripple currents associated with that operating condition. See the Typical Applications section for synchronization examples. The LTM4611 minimum on-time is limited to 90ns. Guardband the on-time to 130ns. The on-time can be calculated as: t ON(MIN)= 1 V OUT * FREQ VIN
Output Voltage Tracking and Soft-Start Functions Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. The master regulator's output is divided down with an external resistor divider that is the same as the slave regulator's feedback divider to implement coincident tracking. The LTM4611 uses an accurate 60.4k resistor internally for the top feedback resistor. Figure 4 shows an example of coincident tracking. 60.4k * V TRACK VOUT _ SLAVE = 1+ RFB2 V TRACK is the track ramp applied to the slave's track pin. V TRACK has a control range of 0V to 0.8V, or the internal reference voltage. When the master's output is divided down with the same resistor values used to set the slave's output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave's regulation point. Voltage tracking is disabled when V TRACK is more than 0.8V. RTA in Figure 4 will be equal to the RFB2 for coincident tracking. The TRACK/SS pin of the master can be controlled by an external ramp or the soft-start function of that regulator can be used to develop that master ramp. The LTM4611 can be used as a master by setting the ramp rate on its track pin using a soft-start capacitor. A 1.4A current source is used to charge the soft-start capacitor. The following equation can be used: C t SOFTSTART = 0.8V * SS 1.4A
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300 SWITCHING FREQUENCY 250 PLLFLTR/fSET VOLTAGE 0.41 200 1 10 100 0.1 VALUE OF RESISTOR ON PLLFLTR/fSET PIN (M )
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Figure 3. Relationship Between Oscillator Frequency, PLLFLTR/fSET Voltage, and External RISET Value and Connection
LTM4611 applicaTions inForMaTion
VIN 1.8V TO 5.5V CIN1 22F 10V CIN2 22F 10V CIN3 22F 10V R2 10k SOFT-START CAPACITOR CSS VIN COMP TRACK/SS RUN CONTINUOUS MODE LTM4611 INTVCC PGOOD VOUT VOUT_LCL DIFFVOUT VOSNS+ VOSNS- GND VFB RFB1 69.8k CFF1* CP1* 47pF VOUT 1.5V 15A
+
COUT1* 470F 6.3V
COUT2* 100F 6.3V
PLLFLTR/fSET MODE_PLLIN SGND
VIN 1.8V TO 5.5V
CIN4 22F 10V
CIN5 22F 10V
CIN6 22F 10V R1 10k
MASTER RAMP OR OUTPUT RTA 121k RTB 60.4k COMP
VIN TRACK/SS RUN
INTVCC PGOOD VOUT LTM4611 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- GND VFB RFB2 121k CFF2* CP2* 47pF
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+
COUT3* 470F 6.3V
COUT4* 100F 6.3V
VOUT 1.2V 15A
CONTINUOUS MODE
PLLFLTR/fSET MODE_PLLIN SGND
*SEE TABLE 5
Figure 4. Dual Outputs (1.5V and 1.2V) With Tracking
MASTER OUTPUT OUTPUT VOLTAGE
SLAVE OUTPUT
minimum to 9.8ms maximum. Tracking a rail in a manner such that TRACK/SS ramps up at a rate faster than 210V/s may also warrant special attention, as explained in the following. Faster turn-on and tracking rates are achievable, if needed: one need only decrease the default PLLFLTR/fSET RC time constant. Recall that the PLLFLTR/fSET pin is biased to 1.23V via a high impedance source (>350k); also be aware that the internal PLL filter contains an initially discharged 10nF capacitor prior to INTVCC being established. Requiring the output voltage to power up rapidly without attention to the PLLFLTR/fSET time-constant results in an initial switching frequency of operation that is initially lower than expected (~250kHz)--only during the early stages of start-up--until the PLLFLTR/fSET voltage reaches steady-state value (1.23V by default).
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TIME
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Figure 5. Output Voltage Coincident Tracking
Even for applications that do not require tracking or sequencing, a minimum recommended value for CSS is 10nF (X7R MLCC, 10% tolerance, nominal; X5R material may be substituted if the capacitor temperature will not exceed 85C), yielding extreme turn-on rise times of 3.8ms
LTM4611 applicaTions inForMaTion
Decreasing the PLLFLTR/fSET RC time constant can be accomplished, for example, by driving the PLLFLTR/fSET pin with an external, lower impedance resistor divider network from INTVCC and GND to PLLFLTR/fSET--in the simplest of implementations, by shorting PLLFLTR/fSET to INTVCC (thereby programming the switching frequency to 780kHz, nominal), or by driving the PLLFLTR/fSET pin from a low impedance voltage source. When, in addition to needing faster turn-on time, one is also synchronizing to an external clock signal, one need bear in mind: the PLL's sink and source current is recommended for not more than 8A loading, and the PLL will need to successfully drive any external PLLFLTR/fSET network impedance to achieve phase lock; and lastly, some phase shift in clock synchronization will occur as external loading on PLLFLTR/fSET becomes heavier. To be clear, using a CSS value of 10nF (or higher) eliminates the need for any of the above special considerations or provisions. Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master's TRACK/SS pin. As mentioned above, the TRACK/SS pin has a control range from 0V to 0.8V. The master's TRACK/SS pin slew rate is directly equal to the master's output slew rate in volts/time. The equation: MR * 60.4k = R TB SR where MR is the master's output slew rate and SR is the slave's output slew rate in volts/time. When coincident tracking is desired, then MR and SR are equal, thus RTB is equal to 60.4k. RTA is derived from equation: R TA = 0.8V V V V FB + FB - TRACK 60.4k RFB2 R TB In ratiometric tracking, a different slew rate maybe desired for the slave regulator. RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach its final value before the master output. For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then RTB = 75k. Solve for RTA to equal to 87k. Beware that without any kind of soft-start ramp up, it is important to provide thorough input filter capacitance to handle input surge currents at start-up, so as to avoid excessive input line sag and power supply motor boating. Leaving provision for at least a soft-start capacitor in one's application is strongly recommended. Overcurrent and Overvoltage Protection The LTM4611 has overcurrent protection (OCP) in a short circuit. The internal current comparator threshold folds back during a short to reduce the output current. An overvoltage condition (OVP) above 7.5% of the regulated output voltage will force the top MOSFET off and the bottom MOSFET on until the condition is cleared. An input electronic circuit breaker or fuse can be sized to be tripped or cleared when the bottom MOSFET is turned on to protect against the overvoltage. Foldback current limiting is disabled during soft-start or tracking start-up. Run Enable The RUN pin is used to enable the power module or sequence the power module. The threshold is 1.22V. The RUN pin must be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: R2 = R1 VUVLO -1 1.22V
where VFB is the feedback voltage reference of the regulator, and V TRACK is 0.8V. Since RTB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then RTA is equal to RFB2 with VFB = V TRACK. Therefore RTB = 60.4k, and RTA = 121k in Figure 4.
To achieve the lowest possible UVLO, 1.22V, leave R2 unpopulated. R1 can be 10k, or if R2 is unpopulated, R1 may be replaced with a hardwired connection from VIN to RUN.
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LTM4611 applicaTions inForMaTion
See the Block Diagram for the example of use. When RUN is below its threshold, TRACK/SS is pulled low by internal circuity. INTVCC Regulator The LTM4611 has an internally regulated bias supply called INTVCC. This regulator output has a 4.7F ceramic capacitor internal. This regulator powers the internal controller and MOSFET drivers. The gate driver current is ~13mA for 500kHz operation and ~20mA for 780kHz operation; the regulator loss is ~40mW and ~60mW, respectively. Stability Compensation The module has already been internally compensated for all output voltages. Table 5 is provided for most application requirements. The Linear Technology Module Power Design Tool will be provided for other control loop optimization. Thermal Considerations and Output Current Derating The LTM4611 output current may need to be derated if it is required to operate in a high ambient temperature or deliver a large amount of continuous power. Some factors that influence derating are input voltage, output power, ambient temperature, airflow, and elevation (air density). The power loss curves in Figures 7 to 9 and current derating curves in Figures 10 to 16 can be used as a guide. These curves were generated by an LTM4611 mounted to a 95mm x 76mm 4-layer FR4 printed circuit board (PCB) 1.6mm thick with two ounce copper for the outer layers and one ounce copper for the two inner layers. Boards of other sizes and layer count can exhibit different thermal behavior, so it is ultimately incumbent upon the user to verify proper operation over the intended system's line, load and environmental operating conditions. The thermal resistance numbers listed in the Pin Configuration section of the data sheet are based on modeling the Module package mounted on a test board specified per JESD51-9 ("Test Boards for Area Array Surface Mount Package Thermal Measurements"). The thermal coefficients provided are based on JESD 51-12 ("Guidelines for Reporting and Using Electronic Package Thermal Information"). For increased accuracy and fidelity to the actual application, many designers use finite element analysis (FEA) to predict thermal performance. To that end, the Pin Configuration section of the data sheet typically gives four thermal coefficients: 1. JA: thermal resistance from junction to ambient. 2. JCbottom: thermal resistance from junction to the bottom of the product case. 3. JCtop: thermal resistance from junction to top of the product case. 4. JB: thermal resistance from junction to the printed circuit board. While the meaning of each of these coefficients may seem to be intuitive, JEDEC has defined each to avoid confusion and inconsistency. These definitions are given in JESD 51-12, and are quoted or paraphrased in the following: 1. JA is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as "still air" although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not necessarily reflect an actual application or viable operating condition. 2. JCbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical Module, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don't generally match the user's application. 3. JCtop is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical Module are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of JCbottom, this value may be useful for comparing packages but the test conditions don't generally match the user's application.
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LTM4611 applicaTions inForMaTion
4. JB is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the Module and into the board, and is really the sum of the JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. Given these definitions, it should now be apparent that none of these thermal coefficients reflects an actual physical operating condition of a Module. Thus, none of them can be individually used to accurately predict the thermal performance of the product. Likewise, it would be inappropriate to attempt to use any one coefficient to correlate to the junction temperature versus load graphs given in the product's data sheet. The only appropriate way to use the coefficients is to run a detailed thermal analysis, such as FEA, which considers all of the thermal resistances simultaneously. A graphical representation of these thermal resistances is given in Figure 5. The blue resistances are contained within the Module, and the green are outside. The die temperature of the LTM4611 must be lower than the maximum rating of 125C, so care should be taken in the layout of the circuit to ensure good heat sinking of the LTM4611. The bulk of the heat flow out of the LTM4611 is through the bottom of the module and the LGA pads into the printed circuit board. Consequently, a poor printed circuit board design can cause excessive heating, resulting in impaired performance or reliability. Please refer to the PCB Layout section for printed circuit board design suggestions The 1.2V, 2.5V and 3.3V power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to 16 for calculating an approximate JA thermal resistance for the LTM4611 with various heat sinking and air flow conditions, as evaluated on the aforementioned 4-layer FR4 PCB. The power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient temperature. These approximate factors are: 1 up to 50C; 1.1 for 60C; 1.15 for 70C; 1.2 for 80C; 1.25 for 90C; 1.3 for 100C; 1.35 for 110C and 1.4 for 120C. The derating curves are plotted with the output current starting at 15A and the ambient temperature at 55C. The output voltages are 1.2V, 2.5V and 3.3V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without air flow, and with and without a heat sink attached with thermally conductive adhesive tape. The BGA heat sinks evaluated in Table 5 yield very comparable performance in laminar airflow despite being visibly different in construction and form factor. The power loss increase with
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD) JUNCTION-TO-CASE (TOP) RESISTANCE CASE (TOP)-TO-AMBIENT RESISTANCE
JUNCTION
JUNCTION-TO-BOARD RESISTANCE JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD (BOTTOM) RESISTANCE RESISTANCE BOARD-TO-AMBIENT RESISTANCE
At
MODULE
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Figure 6
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LTM4611 applicaTions inForMaTion
4.0 3.5 3.0 POWER LOSS (W) 2.5 2.0 1.5 1.0 0.5 0 0 3 12 9 OUTPUT CURRENT (A) 6 15
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MAXIMUM LOAD CURRENT (A)
POWER LOSS (W)
5VIN 3.3VIN 2.5VIN 1.8VIN 1.5VIN
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0
5VIN TO 2.5VOUT 5VIN TO 3.3VOUT 3.3VIN TO 2.5VOUT
16 14 12 10 8 6 4 2 400LFM 200LFM 0LFM 55 65 75 95 105 115 85 AMBIENT TEMPERATURE (C) 125
3
12 9 OUTPUT CURRENT (A)
6
15
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0
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Figure 7. 1.2VOUT Power Loss
16
Figure 8. 2.5VOUT and 3.3VOUT Power Loss
16 14 MAXIMUM LOAD CURRENT (A) 12 10 8 6 4 2 125 0 55 65 400LFM 200LFM 0LFM 95 105 115 85 AMBIENT TEMPERATURE (C) 75 125 MAXIMUM LOAD CURRENT (A)
Figure 9. 5VIN to 1.2VOUT No Heat Sink
16 14 12 10 8 6 4 2 0 55 65 400LFM 200LFM 0LFM 75 95 105 115 85 AMBIENT TEMPERATURE (C) 125
14 MAXIMUM LOAD CURRENT (A) 12 10 8 6 4 2 0 55 65 400LFM 200LFM 0LFM 95 105 115 85 AMBIENT TEMPERATURE (C) 75
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Figure 10. 5VIN to 1.2VOUT with Heat Sink Figure 11. 3.3VIN to 1.2VOUT No Heat Sink Figure 12. 3.3VIN to 1.2VOUT with Heat Sink
16 14 MAXIMUM LOAD CURRENT (A) MAXIMUM LOAD CURRENT (A) 12 10 8 6 4 2 0 55 65 400LFM 200LFM 0LFM 95 105 115 85 AMBIENT TEMPERATURE (C) 75 125 16 14 12 10 8 6 4 2 0 55 65 400LFM 200LFM 0LFM 95 105 115 85 AMBIENT TEMPERATURE (C) 75 125 MAXIMUM LOAD CURRENT (A) 16 14 12 10 8 6 4 2 0 55 65 400LFM 200LFM 0LFM 75 95 105 115 85 AMBIENT TEMPERATURE (C) 125
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Figure 13. 3.3VIN to 2.5VOUT No Heat Sink Figure 14. 3.3VIN to 2.5VOUT with Heat Sink
Figure 15. 5VIN to 3.3VOUT No Heat Sink
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LTM4611 applicaTions inForMaTion
16 14 MAXIMUM LOAD CURRENT (A) 12 10 8 6 4 2 0 55 65 400LFM 200LFM 0LFM 75 95 105 115 85 AMBIENT TEMPERATURE (C) 125
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Figure 16. 5VIN to 3.3VOUT with Heat Sink Table 2. 1.2V Output
DERATING CURVE Figures 9, 11 Figures 9, 11 Figures 9, 11 Figures 10, 12 Figures 10, 12 Figures 10, 12 VIN 5V, 3.3V 5V, 3.3V 5V, 3.3V 5V, 3.3V 5V, 3.3V 5V, 3.3V POWER LOSS CURVE Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7
ambient temperature change is factored into the derating curves. The junctions are maintained at 115C maximum while lowering output current or power while increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 115C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 11, the load current is derated to ~12A at ~75C with no air or heat sink and the power loss for the 3.3V to 1.2V at 12A output is a 2.82W loss. The 2.82W loss is calculated with the ~2.4W room temperature loss from the 3.3V to 1.2V power loss curve at 12A (Figure 7), and the 1.175 multiplying factor at 75C ambient. If the
AIR FLOW (LFM) 0 200 400 0 200 400
HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink
JA (C/W) 14 11.5 10.6 11.5 8.4 7.5
Table 3. 2.5V Output
DERATING CURVE Figures 13 Figures 13 Figures 13 Figures 14 Figures 14 Figures 14 VIN 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V POWER LOSS CURVE Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 AIR FLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink JA (C/W) 15.5 12.7 12.1 12.6 10.6 8.9
Table 4. 3.3V Output
DERATING CURVE Figures 15 Figures 15 Figures 15 Figures 16 Figures 16 Figures 16 VIN 5V 5V 5V 5V 5V 5V POWER LOSS CURVE Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 Figure 8 AIR FLOW (LFM) 0 200 400 0 200 400 HEAT SINK None None None BGA Heat Sink BGA Heat Sink BGA Heat Sink JA (C/W) 14 11.5 10.2 12 10.1 9.3
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0
LTM4611 applicaTions inForMaTion
75C ambient temperature is subtracted from the 115C junction temperature, then the difference of 40C divided by 2.82W yields a thermal resistance, JA, of 14.2C/W--in good agreement with Table 2. Tables 2, 3 and 4 provide equivalent thermal resistances for 1.2V, 2.5V and 3.3V outputs with and without air flow and heat sinking. The derived thermal resistances in Tables 2, 3 and 4 for the
TYPICAL MEASURED VALUES PART NUMBER COUT1 VENDORS AVX 12106D107MAT2A (100F, 6.3V, 1210 Case Size) Taiyo Yuden JMK325BJ107MM-T (100F, 6.3V, 1210 Case Size) TDK C3225X5R0J107MT (100F, 6.3V, 1210 Case Size) AVX 1206D226MAT (22F, 6.3V, 1206 Case Size) Taiyo Yuden JMK316BJ226ML-T (22F, 6.3V, 1206 Case Size) TDK C3216X5R0J226MT (22F, 6.3V, 1206 Case Size)
various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors.
Table 5. Output Voltage Response Versus Component Matrix, 0A to 7.5A Load Step
COUT2 VENDORS Sanyo POSCAP Sanyo POSCAP PART NUMBER 6TPF330M9L (330F, 6.3V, 9m ESR, D3L Case Size) 2R5TPE470M9 (470F, 2.5V, 9m ESR, D2E Case Size)
VOUT (V) 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 1 1 1 1 1 1 1 1 1 1 1 1.2 1.2 1.2 1.2 1.2 1.2 1.2
VIN CIN* CIN* (V) (CERAMIC) (BULK) 1.5 2 x 47F 470F 1.5 2 x 47F 470F 1.8 2 x 47F 220F 1.8 2 x 47F 220F 1.8 2 x 47F 220F 2.5 2 x 47F 150F 2.5 2 x 47F 150F 3.3 2 x 47F 150F 3.3 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 1.5 2 x 47F 680F 1.5 2 x 47F 680F 1.8 2 x 47F 330F 1.8 2 x 47F 330F 1.8 2 x 47F 330F 2.5 2 x 47F 150F 2.5 2 x 47F 150F 3.3 2 x 47F 150F 3.3 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 1.5 2 x 47F 1000F 1.5 2 x 47F 1000F 1.8 2 x 47F 470F 1.8 2 x 47F 470F 1.8 2 x 47F 470F 2.5 2 x 47F 220F 2.5 2 x 47F 220F
TRANSIENT LOAD DROOP, TRANSIENT STEP USING 0A TO 7.5A PEAK-TO-PEAK, SLEW DIFF LOAD STEP 0A TO 7.5A TO 0A RECOVERY RATE RSET COUT2 COUT1 AMP FIGURE (mV) (mVP-P) (CERAMIC) (BULK) CFF CP TIME (s) (A/s) (k) Y 21 65 118 15 7.5 481 5 x 100F None 220pF None 470F 22pF None Y 21 63 122 25 7.5 481 3 x 22F Y 21 65 119 20 7.5 481 4 x 100F None 220pF None 470F 47pF None Y 21 60 113 25 7.5 481 3 x 22F Y 21 64 119 30 7.5 481 4 x 22F 330F 22pF None None 33pF 10pF Y 21 54 108 20 7.5 481 5 x 100F Y 21 65 123 20 7.5 481 7 x 22F 330F None 22pF None 47pF None Y 21 50 104 25 7.5 481 4 x 100F Y 21 55 109 20 7.5 481 7 x 22F 330F 10pF 10pF None 47pF None Y 21 47 102 20 7.5 481 4 x 100F 330F 10pF 10pF Y 21 61 116 20 7.5 481 6 x 22F Y 21 70 128 20 7.5 243 5 x 100F None 220pF None 470F 33pF None Y 21 62 121 25 7.5 243 3 x 22F None 220pF None Y 21 68 123 20 7.5 243 4 x 100F 470F 33pF None Y 21 60 115 30 7.5 243 3 x 22F 330F 22pF None Y 21 66 123 30 7.5 243 4 x 22F 47pF None Y 21 61 115 25 7.5 243 4 x 100F None Y 21 63 115 25 7.5 243 7 x 22F 330F 10pF 10pF 47pF None Y 21 52 106 30 7.5 243 4 x 100F None Y 21 57 111 20 7.5 243 7 x 22F 330F 10pF 10pF 47pF None Y 21 53 108 25 7.5 243 4 x 100F None Y 21 62 119 25 7.5 243 6 x 22F 330F 10pF 10pF Y 21 82 145 20 7.5 121 6 x 100F None 220pF None Y 21 70 133 30 7.5 121 2 x 22F 470F 47pF None Y 21 75 136 25 7.5 121 4 x 100F None 220pF None Y 21 64 126 30 7.5 121 3 x 22F 470F 22pF None Y 21 72 137 30 7.5 121 4 x 22F 330F 22pF None Y 21 58 114 30 7.5 121 4 x 100F None 100pF None Y 21 65 122 25 7.5 121 5 x 22F 330F 10pF 10pF
4611f
LTM4611 applicaTions inForMaTion
VOUT (V) 1.2 1.2 1.2 1.2 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.8 1.8 1.8 1.8 1.8 1.8 2.5 2.5 2.5 2.5 2.5 2.5 3.3 3.3 3.3 3.3 5 5 VIN CIN* CIN* (V) (CERAMIC) (BULK) 3.3 2 x 47F 150F 3.3 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 1.8 2 x 47F 1000F 1.8 2 x 47F 1000F 2.5 2 x 47F 220F 2.5 2 x 47F 220F 3.3 2 x 47F 150F 3.3 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 2.5 2 x 47F 330F 2.5 2 x 47F 330F 3.3 2 x 47F 150F 3.3 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 3.3 2 x 47F 330F 3.3 2 x 47F 330F 3.3 2 x 47F 330F 5 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 5 2 x 47F 150F 5.5 2 x 47F 680F 5.5 2 x 47F 680F COUT2 (CERAMIC) 4 x 100F 7 x 22F 4 x 100F 6 x 22F 6 x 100F 2 x 22F 4 x 100F 5 x 22F 4 x 100F 4 x 22F 4 x 100F 6 x 22F 4 x 100F 5 x 22F 4 x 100F 4 x 22F 4 x 100F 6 x 22F 3 x 100F 4 x 100F 3 x 22F 3 x 100F 4 x 100F 5 x 22F 2 x 100F 3 x 100F 4 x 100F 5 x 22F 1 x 100F 7 x 22F COUT1 (BULK) None 330F None 330F None 470F None 330F None 330F None 330F None 330F None 330F None 330F None None 330F None None 330F None None None 330F None None TRANSIENT LOAD DROOP, TRANSIENT STEP USING 0A TO 7.5A PEAK-TO-PEAK, SLEW DIFF LOAD STEP 0A TO 7.5A TO 0A RECOVERY RATE RSET AMP FIGURE (mV) (mVP-P) CP TIME (s) (A/s) (k) 10pF Y 21 60 116 30 7.5 121 10pF Y 21 63 117 20 7.5 121 None Y 21 47 105 30 7.5 121 10pF Y 21 64 123 25 7.5 121 None Y 21 83 147 25 7.5 69 None Y 21 71 135 40 7.5 69 None Y 21 64 122 40 7.5 69 10pF Y 21 68 133 30 7.5 69 10pF Y 21 66 123 30 7.5 69 None Y 21 67 124 30 7.5 69 10pF Y 21 59 122 30 7.5 69 10pF Y 21 67 131 30 7.5 69 None Y 21 73 137 45 7.5 48.1 None Y 21 76 145 35 7.5 48.1 10pF Y 21 57 118 40 7.5 48.1 None Y 21 69 137 30 7.5 48.1 10pF Y 21 64 127 40 7.5 48.1 10pF Y 21 69 133 30 7.5 48.1 None Y 21 71 143 45 7.5 28.4 None Y 21 66 123 40 7.5 28.4 None Y 21 67 128 50 7.5 28.4 None Y 21 60 134 45 7.5 28.4 None Y 21 54 115 50 7.5 28.4 None Y 21 81 160 40 7.5 28.4 None Y 21 137 274 40 7.5 19.3 None Y 21 67 143 50 7.5 19.3 None Y 21 56 119 60 7.5 19.3 None Y 21 95 193 45 7.5 19.3 None N 20 264 511 30 7.5 11.5 None N 20 218 431 40 7.5 11.5 WEBSITE www.wakefield.com www.aavidthermalloy.com
CFF 33pF 10pF 47pF 10pF 220pF 47pF 220pF 22pF 33pF 22pF 33pF None 220pF 22pF 47pF 22pF 33pF None 100pF 100pF 47pF 100pF 100pF 22pF 22pF 47pF 100pF 22pF 10pF None
HEAT SINK MANUFACTURER Wakefield Engineering AAVID Thermalloy THERMALLY CONDUCTIVE ADHESIVE TAPE MANUFACTURER Chromerics
PART NUMBER LTN20069 375424B00034G
PART NUMBER T411
WEBSITE www.chromerics.com
*The quantity and quality of bulk input bypass capacitance needed, particularly for low dropout scenarios (VIN - VOUT < 600mV) is mainly dependent on the output impedance and dynamic response of the power source feeding the LTM4611(s). Consider, in the extreme: for a heavy load step, the full transient on LTM4611's output is directly
referred to its input, and the LTM4611 can only deliver to its output whatever the source supply and local input caps can provide. Sluggish source supplies will call for more bulk capacitance placed locally to the LTM4611's input, to assist the source supply in riding through severe transient load steps.
4611f
LTM4611 applicaTions inForMaTion
Safety Considerations The LTM4611 modules do not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The device does support overvoltage protection and overcurrent protection. Layout Checklist/Example The high integration of LTM4611 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. * Use large PCB copper areas for high current paths, including VIN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. * Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize high frequency noise. * Place a dedicated power ground layer underneath the unit. * To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. * Do not put vias directly on the pad, unless they are capped or plated over. * Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit. * For parallel modules, tie the respective COMP, VFB, VOUT_LCL, TRACK/SS and RUN pins together. Use an internal layer to closely connect these pins together. Figure 17 gives a good example of the recommended layout. Figures 18 and 19 show schematics of the LTM4611 devices operating in parallel. * To facilitate stuffing verification, test and debug activities, consider routing control signals of the LTM4611 with short traces to localized test points, test pads or test vias-as PCB layout space permits. Both in-house and contract manufacturers enjoy gaining electrical access to all non low impedance (>10) pins of an IC or Module device to improve in-circuit test (ICT) coverage.
VIN CIN CIN CONTROL
CONTROL
GND
SIGNAL GROUND
CONTROL
COUT VOUT
COUT VOUT
4611 F17
Figure 17. Recommended PCB Layouts
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LTM4611 Typical applicaTions
VIN 1.5V TO 5.5V R1 10k CIN1 22F 10V CIN2 22F 10V C SS 0.1F INTVCC VIN COMP TRACK/SS RUN LTM4611 PLLFLTR/fSET MODE_PLLIN SGND INTVCC C1 1F 4-PHASE CLOCK V+ SET CIN3 22F 10V CIN4 22F 10V COMP TRACK/SS RUN LTM4611 PLLFLTR/fSET MODE_PLLIN SGND GND R2 100k GND INTVCC PGOOD VOUT VOUT_LCL DIFFVOUT VOSNS+ VOSNS- VFB RFB 30.1k CFF1* VOUT 1.2V 60A
+
COUT1* 470F 6.3V
COUT2* 100F 6.3V
CP1*
LTC6902 MOD DIV PH OUT1 OUT2 GND OUT4 OUT3
VIN
INTVCC PGOOD VOUT VOUT_LCL DIFFVOUT VOSNS+ VOSNS- VFB INTVCC CP2* CFF2*
+
COUT3* 470F 6.3V
COUT4* 100F 6.3V
CIN5 22F 10V
CIN6 22F 10V COMP
VIN TRACK/SS RUN
INTVCC PGOOD VOUT VOUT_LCL DIFFVOUT VOSNS+ VOSNS- GND VFB INTVCC CP3* CFF3*
+
LTM4611 PLLFLTR/fSET MODE_PLLIN SGND
COUT5* 470F 6.3V
COUT6* 100F 6.3V
CIN7 22F 10V
CIN8 22F 10V COMP
VIN TRACK/SS RUN
INTVCC PGOOD VOUT VOUT_LCL DIFFVOUT VOSNS+ VOSNS- GND VFB INTVCC CP4*
4611 F18
CFF4*
+
LTM4611 PLLFLTR/fSET MODE_PLLIN SGND
COUT7* 470F 6.3V
COUT8* 100F 6.3V
*FOR BEST NOISE IMMUNITY, DISTRIBUTE CAPACITORS WITH VFB CONNECTIONS AMONGST ALL PARALLELED LTM4611s
Figure 18. 1.2V, 60A, Current Sharing with 4-Phase Operation
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LTM4611 Typical applicaTions
VIN 1.5V TO 5.5V CIN1 22F 10V CIN2 22F 10V CIN3 22F 10V CSS 0.1F R1 10k INTVCC OUT1 LTC6908-1 OUT2 GND V SET MOD
+
INTVCC
VIN COMP TRACK/SS RUN
INTVCC PGOOD VOUT LTM4611 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- GND VFB RFB 121k CFF1*
+
COUT1* 470F 6.3V
COUT2* 100F 6.3V
VOUT 1V 30A
CLOCK SYNC 0 PHASE
PLLFLTR/fSET MODE_PLLIN SGND
C1 1F R2 200k
CP1*
CIN4 22F 10V
CIN5 22F 10V
CIN6 22F 10V COMP
VIN TRACK/SS RUN
INTVCC PGOOD VOUT LTM4611 VOUT_LCL DIFFVOUT VOSNS+ VOSNS- GND VFB CP2*
4611 F19
CFF2*
+
COUT3* 470F 6.3V
COUT4* 100F 6.3V
CLOCK SYNC 180 PHASE
PLLFLTR/fSET MODE_PLLIN SGND
INTVCC
*FOR BEST NOISE IMMUNITY, DISTRIBUTE CAPACITORS WITH VFB CONNECTIONS AMONGST ALL PARALLELED LTM4611s
Figure 19. 1V at 30A LTM4611 Two Parallel Outputs with 2-Phase Operation
5V
CIN1 22F 10V
CIN2 22F 10V
CIN3 22F 10V R1 10k
CSS 0.1F
VIN COMP TRACK/SS RUN
INTVCC PGOOD VOUT VOUT_LCL LTM4611 DIFFVOUT VOSNS+ VOSNS- GND VFB INTVCC RFB 19.1k CFF*
+
COUT1* 220F 6.3V
COUT2* 47F 6.3V
3.3V 15A
PLLFLTR/fSET CONTINUOUS MODE MODE_PLLIN SGND
C P*
4611 F20
*SEE TABLE 5
Figure 20. 3.3V at 15A Design, Example of Not Using Differential Remote Sense
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LTM4611 package phoTograph
package DescripTion
Pin Assignment Table (Arranged by Pin Number)
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 PIN NAME VIN VIN VIN VIN VIN VIN INTVCC MODE_PLLIN TRACK/SS RUN COMP MTP1 PIN NAME GND GND GND GND GND GND GND GND GND SGND PGOOD B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 PIN NAME VIN VIN VIN VIN VIN VIN GND GND MTP2 PLLFLTR/f SET PIN NAME GND GND GND GND GND GND GND GND GND SGND SGND PIN NAME C1 VIN C2 VIN C3 VIN C4 VIN C5 VIN C6 VIN C7 GND C8 C9 GND C10 MTP3 C11 MTP4 C12 MTP5 PIN NAME J1 VOUT J2 VOUT J3 VOUT J4 VOUT J5 VOUT J6 VOUT J7 VOUT J8 VOUT J9 VOUT J10 VOUT J11 J12 VOSNS+ PIN NAME D1 GND D2 GND D3 GND D4 GND D5 GND D6 GND D7 D8 GND D9 INTVCC D10 MTP6 D11 MTP7 D12 MTP8 PIN NAME K1 VOUT K2 VOUT K3 VOUT K4 VOUT K5 VOUT K6 VOUT K7 VOUT K8 VOUT K9 VOUT K10 VOUT K11 VOUT K12 DIFFVOUT PIN NAME E1 GND E2 GND E3 GND E4 GND E5 GND E6 GND E7 GND E8 E9 GND E10 E11 E12 MTP9 PIN NAME L1 VOUT L2 VOUT L3 VOUT L4 VOUT L5 VOUT L6 VOUT L7 VOUT L8 VOUT L9 VOUT L10 VOUT L11 VOUT L12 VOUT_LCL PIN NAME F1 GND F2 GND F3 GND F4 GND F5 GND F6 GND F7 GND F8 GND F9 GND F10 F11 PGOOD F12 V FB PIN NAME M1 VOUT M2 VOUT M3 VOUT M4 VOUT M5 VOUT M6 VOUT M7 VOUT M8 VOUT M9 VOUT M10 VOUT M11 VOUT M12 VOSNS -
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12
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LGA Package 133-Lead (15mm x 15mm x 4.32mm)
(Reference LTC DWG # 05-08-1777 Rev O)
DETAIL A 15 BSC X Y 12 11 10 9 8 15 BSC MOLD CAP SUBSTRATE 13.97 BSC 7 6 5 4 3 2 aaa Z PADS SEE NOTES 3 0.630 1.9050 3.1750 4.4450 5.7150 6.9850 0.630 0.025 SQ. 133x eee S X Y DETAIL B M L K J H G F E D C B A 1 C(0.30) PAD 1 4.22 - 4.42 13.97 BSC 0.12 - 0.28
package DescripTion
aaa Z
0.27 - 0.37 3.95 - 4.05 DETAIL B bbb Z Z
PAD 1 CORNER
1.27 BSC
4
PACKAGE TOP VIEW
PACKAGE BOTTOM VIEW
6.9850
5.7150
4.4450
3.1750
1.9050
6.9850
5.7150 0.630 DETAIL A
4.4450
3.1750
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 4 LAND DESIGNATION PER JESD MO-222, SPP-010
LTMXXXXXX Module
COMPONENT PIN "A1"
1.9050
0.6350 0.0000 0.6350
1.9050
3.1750
4.4450
0.6350 0.0000 0.6350
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE
5.7150
5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 SYMBOL TOLERANCE aaa 0.15 bbb 0.10 eee 0.05
6.9850
TRAY PIN 1 BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
LGA 133 1008 REV O
LTM4611
SUGGESTED PCB LAYOUT TOP VIEW
4611f
LTM4611 Typical applicaTion
VIN 1.5V TO 5.5V* CIN1 22F 10V CIN2 22F 10V CIN3 22F 10V R1 10k INTVCC CSS 0.1F VIN COMP TRACK/SS RUN CONTINUOUS MODE LTM4611 INTVCC PGOOD VOUT VOUT_LCL DIFFVOUT VOSNS+ VOSNS- GND VFB RFB 240k CP*
4611 F21
CFF*
+
COUT1* 220F 6.3V
VOUT 1V COUT2* 15A 22F 6.3V 2
PLLFLTR/fSET MODE_PLLIN SGND
*SEE TABLE 5
Figure 21. 1.5V to 5.5VIN, 1V at 15A Design
relaTeD parTs
PART NUMBER LTM4600 LTM4601A LTM4602 LTM4603 LTM4604A LTM4605 LTM4606 LTM4607 LTM4608A LTM4609 LTM4612 LTM8023 LTM8032 DESCRIPTION 10A DC/DC Module 12A DC/DC Module with PLL, Output Tracking/ Margining and Remote Sensing 6A DC/DC Module 6A DC/DC Module with PLL and Output Tracking/ Margining and Remote Sensing 4A Low Voltage DC/DC Module Buck-Boost DC/DC Module Family Ultralow Noise 6A DC/DC Module Buck-Boost DC/DC Module Family 8A Low Voltage DC/DC Module Buck-Boost DC/DC Module Family Ultralow Noise High VOUT DC/DC Module 36V, 2A DC/DC Module Ultralow Noise 36V, 2A DC/DC Module COMMENTS Basic 10A DC/DC Module Synchronizable, PolyPhase Operation to 48A, Pin Compatible with the LTM4611 and LTM4617 Pin Compatible with the LTM4600 Synchronizable, PolyPhase Operation, LTM4603-1 Version has no Remote Sensing, Pin Compatible with the LTM4601 2.375V VIN 5.5V; 0.8V VOUT 5V, 9mm x 15mm x 2.3mm (Ultrathin) LGA Package All Pin Compatible; Up to 5A; Up to 36VIN, 34VOUT 15mm x 15mm x 2.8mm 4.5V VIN 28V, 0.6V VOUT 5V, 15mm x 15mm x 2.8mm Package All Pin Compatible; Up to 5A; Up to 36VIN, 34VOUT 15mm x 15mm x 2.8mm 2.7V VIN 5.5V; 0.6V VOUT 5V; 9mm x 15mm x 2.8mm LGA Package All Pin Compatible; Up to 5A; Up to 36VIN, 34VOUT 15mm x 15mm x 2.8mm 5A, 5V VIN 36V, 3.3V VOUT 15V, 15mm x 15mm x 2.8mm Package 3.6V VIN 36V, 0.8V VOUT 10V, 9mm x 11.25mm x 2.8mm Package EN55022 Class B Compliant; 0.8V VOUT 10V; 3.6V VIN 36V; 9mm x 15mm x 2.8mm
4611f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
LT 0510 * PRINTED IN USA
FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010

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